----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    
-- Design Name: 
-- Module Name:    T2p18 - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;

entity CB8CE is  -- free running binary up-counter
  port(
    CLR, CLK, CE: in std_logic;
    Q: out std_logic_vector(7 downto 0);
    TC: out std_logic
  );
end CB8CE;

architecture arch of CB8CE is
  signal r_reg: unsigned(7 downto 0);
  signal r_next: unsigned(7 downto 0);
begin
  -- register
  process(CLK, CLR)
  begin
    if (CLR='1') then
      r_reg <= (others=>'0');
    elsif (CLK'event and CLK='1') then
	   if CE='1' then
        r_reg <= r_next;
		end if;
    end if;
  end process;
  -- next-state logic
  r_next <= r_reg + 1;
  -- output logic
  Q <= std_logic_vector(r_reg);
  TC <= '1' when r_reg=1 else '0';
end arch;

--CB8CE_inst: entity CB8CE -- free running binary up-counter
--  port map(
--    CLR => ,
--    CLK => ,
--    CE  => ,
--    Q   => ,
--    TC  =>
--  );
